1. Field of the Invention
The present invention relates to display device, and more particularly, to a shift register for a display device and a driving method thereof.
2. Discussion of the Related Art
Recently, various flat panel displays that are lighter and less bulky than cathode ray tubes (CRT) have been developed. These flat panel displays include, for example, a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), and a light emitting display (LED). In particular, the LCD includes an LCD panel having liquid crystal cells in a matrix arrangement, and a driving circuit for driving the LCD panel. The LCD displays an image by controlling a light transmittance of the liquid crystal cells using an electric field.
The liquid crystal cells are disposed in pixel regions formed by crossings of gate lines with data lines in the LCD panel. The LCD panel is provided with a common electrode and pixel electrodes for applying an electric field to each of the liquid crystal cells. Each of the pixel electrodes is electrically connected to one of the data lines through source and drain terminals of a switching element, for example, a thin film transistor (TFT).
The TFT used for the LCD includes a semiconductor layer of amorphous silicon or polycrystalline silicon. An amorphous silicon layer provides good uniformity and stable characteristics to the LCD panel. However, it is difficult to improve pixel density in an amorphous type LCD due to its low charge mobility. To overcome such drawbacks, a driving circuit using amorphous silicon has been built into an array substrate.
FIG. 1 illustrates a related art LCD. Referring to FIG. 1, the related art LCD includes an LCD panel 10, a printed circuit board 20, a plurality of tape carrier packages (TCP) 30, and a plurality of data integrated circuits 40. The LCD panel 10 is provided with a gate shift register 50 for supplying gate pulses to an image display unit 12. The printed circuit board 20 is provided with a control circuit (not shown) and a power circuit (not shown). The TCPs 30 are connected between the printed circuit board 20 and the LCD panel 10. The data integrated circuits 40 are respectively provided in the TCPs and supply analog video signals to the image display unit 12.
The image display unit 12 displays images through liquid crystal cells LC arranged in a matrix. Each of the liquid crystal cells LC includes a TFT made of polycrystalline silicon or amorphous silicon as a switching element electrically connected to each crossing of gate lines GL and data lines DL. The data lines DL are supplied with the analog video signals from the data integrated circuits 40. The gate lines GL are supplied with the gate pulses from the gate shift register 50.
Each of the TCPs 30 is electrically connected between the printed circuit board 20 and the LCD panel 10 by a tape automated bonding TAB. Input pads of each TCP 30 are electrically connected to the printed circuit board 20 while output pads of each TCP 30 are electrically connected to the LCD panel 10.
Each of the data integrated circuits 40 is supplied with control signals and data signals from the control circuit through the input pads of each TCP 30 and converts the data signals into analog video signals using the input control signals to supply the analog video signals to the data lines DL of the LCD panel 10 through the output pads of each TCP 30. The gate shift register 50 is directly formed at one side of the LCD panel 10.
FIG. 2 illustrates a gate shift register according to the related art LCD of FIG. 1. The gate shift register 50 includes a plurality of stages 511 to 51n whose output nodes are respectively connected to corresponding gate lines GL1 to GLn. The stages 511 to 51n are respectively connected to a start pulse SP input line and at least one clock signal CLK input line. At least one clock signal CLK is phase-delayed by one clock period. If the number of the clock signals CLK is two, for example, the gate shift register 50 is referred to a two-phase shift register.
FIG. 3 illustrates driving waveforms for the related art gate shift register shown in FIG. 2. Referring to FIG. 3, the gate pulses GP are sequentially supplied to the gate lines GL1, to GLn. Specifically, a first gate pulse GP is applied to the first gate line GL1 in a first time period. A second gate pulse GP is applied to the second gate line GL2 in a second time period following the first time period. So, the gate pulses GP are sequentially applied to the gate lines GL1 to GLn.
Thus, in the related art gate shift register, each of the stages 511 to 51n shifts the start pulse SP by one clock period and output the delayed SP when a clock signal CLK is received. The signal output from each of the stages 511 to 51n of the gate shift register 50 is supplied as a start pulse to the next corresponding stage from 512 to 51n. For example, the output from stage 511 is supplied to state 512, and the output of stage 512 is supplied to stage 513, and so on.
The above-described related art LCD displays a desired images in the image display unit 12 by supplying the analog video signals from the data integrated circuits 40 to the data lines DL and concurrently supplying the gate pulses to the gate lines GL using the gate shift register 50 provided in the LCD panel 10.
In the related art LCD, since all the stages 511 to 51n are connected to the clock signal CLK input line, a load of an output line of the shift register increases, thereby causing errors in operation. Also, in the related art LCD, since the gate pulses are sequentially supplied to the gate lines, it is difficult to perform a divisional scan of the LCD panel 10 and change a scan direction when required.